With the development of integrated circuit technology, the feature size of semiconductor devices is getting smaller and smaller. Current complementary metal-oxide semiconductor (CMOS) devices use a high dielectric-constant (high-k) material as the gate dielectric layer and a metal as the gate electrode (HKMG). However, the reduction of the size of MOS semiconductor devices brings many problems.
One problem is that the use of silicon dioxide as a gate dielectric layer generates a high gate leakage current due to the tunneling effect. In the case of the same equivalent oxide thickness (EOT) a high-k (high dielectric constant) dielectric material has a physical thickness larger than that of a conventional silicon dioxide, thus, a high-k dielectric material is utilized as a gate dielectric layer to reduce the gate leakage current.
Another problem is that the depletion effect of a polysilicon gate and the finite inversion layer capacitance reduce the EOT, thereby reducing the device performance. Thus, a metal gate electrode is used instead of a polysilicon gate to reduce the depletion effect of the polysilicon gate.
In order to satisfy the needs of device designers for multiple threshold voltages, the multiple threshold voltages are implemented by using a body doping process in a conventional method. However, as the device size decreases, the adjustment of the threshold voltages by body doping can lead to degradation and fluctuation of carrier mobility. Therefore, in the case of high-k/metal gate (HKMG) processes, in order to solve the problem of degradation and fluctuation of carrier mobility, a work function adjustment layer has been proposed.
In the prior art, in order to obtain an NMOS device having three different threshold voltages, three work function adjustment layers with three different thicknesses are required. For NMOS devices with relatively high threshold voltages, the thickness of the work function adjustment layer is also relatively large. Therefore, in the case where the trench size of a metal gate is relatively small, after forming a relatively thick work function adjustment layer in the trench, it becomes difficult to deposit a metal material filling the trench to form a metal gate, and the filling effect is poor.
FIGS. 1A to 1F are cross-sectional views illustrating intermediate stages of a semiconductor device in a conventional manufacturing method as known in the prior art.
Referring to FIG. 1A, a substrate 11 is provided, and an interlayer dielectric layer 12 having three trenches is formed on substrate 11. The three trenches may be formed with a part of a gate-last process. For example, dummy gates and dummy gate oxide layers are first formed, then an interlayer dielectric layer is then formed to separate the dummy gates, and a planarization process is performed on the interlayer dielectric layer. Thereafter, the dummy gates and the dummy gate oxide layers are removed to form the three trenches.
Next, gate structures for a high threshold voltage NMOS (HVT NMOS) device, a low threshold NMOS (LVT NMOS) device, and an ultra-threshold voltage NMOS (ULVT NMOS) device are formed in the three trenches, respectively. Herein, a high threshold voltage refers to a threshold voltage higher than a standard threshold voltage, a low threshold voltage refers to a threshold voltage lower than the standard threshold voltage, and an ultra-low threshold voltage refers to a threshold voltage that is lower than the low threshold voltage. The high threshold voltage, the low threshold voltage, and the ultra-low threshold voltage may be arbitrarily referred to as the first, second, and third threshold voltages, respectively. Similarly, a high threshold voltage NMOS device, a low threshold voltage NMOS device, and an ultra-low threshold voltage NMOS device may also be arbitrarily referred to as the first, second, and third NMOS devices.
Referring to FIG. 1A, an interface layer 101 is formed at the bottom of the three trenches. Then, a high-k dielectric layer 102, a cap layer 103, a barrier layer 104, and a first PMOS work function adjustment layer 105 are sequentially formed on interface layer 101.
Next, referring to FIG. 1B, a patterned first photoresist 106 is formed on the structure exposing the trench of the LVT NMOS device. First PMOS work function adjustment layer 105 in the trench of the LVT NMOS device is then removed.
Next, referring to FIG. 1C, first photoresist 106 is removed, and a second PMOS work function adjustment layer 107 is then formed in the three trenches.
Next, referring to FIG. 1D, a patterned second photoresist 108 is formed on the structure of FIG. 1C exposing the trench of the ULVT NMOS device. Second PMOS work function adjustment layer 107 and first PMOS work function adjustment layer 105 in the trench of the ULVT NMOS device are removed.
Next, referring to FIG. 1E, second photoresist 108 is removed, a third PMOS work function adjustment layer 110 is then formed in the three trenches.
Thereafter, referring to FIG. 1F, an NMOS work function adjustment layer 111 and a metal electrode layer 112 are formed in the three trenches.
In the above-described conventional approaches, the structure of the work function adjustment layer in each device is as follows:
The structure of the work function adjustment layer of the HVT NMOS device includes first PMOS work function adjustment layer 105, second PMOS work function adjustment layer 107, third PMOS work function adjustment layer 110, and NMOS work function adjustment layer 111.
The structure of the work function adjustment layer of the LVT NMOS device includes second PMOS work function adjustment layer 107, third PMOS work function adjustment layer 110, and NMOS work function adjustment layer 111.
The structure of the work function adjustment layer of the ULVT NMOS device includes third PMOS work function adjustment layer 110, and NMOS work function adjustment layer 111.
However, for the HVT NMOS device with the highest threshold voltage, the number of layers formed in the trench is also the largest (which includes the three PMOS work function adjustment layers), resulting in a narrow trench, which causes problem in filling the trench, so that the filling effect of the trench is poor. For example, when NMOS work function adjustment layer 111 and metal electrode layer 112 are formed in the trench, since the air gap (space) in the trench is small, the trench may not be completely filled so that voids are formed in the trench, thereby affecting the performance of the device.